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RF2153
2
Typical Applications * PACS Handsets and Base Stations * 3V 1850-1910MHz CDMA PCS Handsets * 3V 1750-1780MHz CDMA PCS Handsets * 3V TDMA PCS Handsets * Spread-Spectrum Systems * Commercial and Consumer Systems
CDMA/TDMA/PACS 1900MHZ 3V POWER AMPLIFIER
2
POWER AMPLIFIERS
Product Description
The RF2153 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 3V CDMA and TDMA handheld digital equipment, spread-spectrum systems, and other applications in the 1750MHz to 1910 MHz band. The device is packaged in a compact 4mmx4mm (LCC). The device's frequency response can be optimized for linear performance in the 1750MHz to 1910MHz band.
4.20 3.95 3.50 3.35 1.50 1.20 0.38 0.40 sq.
1
3.50 3.35 4.20 3.95
2.00
1.50 sq.
0.28 0.13
0.80
ALL SOLDER PAD TOLERANCES P0.05mm
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS
!
Package Style: MP16KO1A
GaAs HBT SiGe HBT
GaAs MESFET Si CMOS
Features * Single 3V Supply * 29dBm Linear Output Power * 30dB Linear Gain * 33% Linear Efficiency CDMA * 40% Linear Efficiency TDMA * On-board Power Down Mode
VCC2
VCC2
VCC2
VCC 14 8 VPD2
1 GND2 VCC1 RFIN 2 3 4 5 GND1
16
15
13 12 RF OUT 11 RF OUT 10 RF OUT
6 VPD1
7 V MODE
BIAS GND
2F0 9
Ordering Information
RF2153 RF2153 PCBA CDMA/TDMA/PACS 1900MHz 3V Power Amplifier Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A18 001114
2-167
RF2153
Absolute Maximum Ratings Parameter
Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Mode Voltage (VMODE)
Rating
+8.0 +4.5 +3.5 +3.5 +10 -30 to +110 -30 to +150
Unit
VDC VDC VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
2
POWER AMPLIFIERS
Control Voltage (VPD) Input RF Power Operating Case Temperature Storage Temperature
Parameter
Overall - CDMA
Usable Frequency Range Typical Frequency Range Small Signal Gain Linear Gain Second Harmonic (including second harmonic trap) Third Harmonic Fourth Harmonic Minimum Linear Output Power (CDMA or TDMA Modulation) Idle Current CDMA Linear Efficiency CDMA Adjacent Channel Power Rejection @ 1.25MHz Minimum Linear Output Power (CDMA Modulation) Input VSWR Output Load VSWR Turn On/Off Time
Specification Min. Typ. Max.
1750 1750-1780 1850-1910 32 29 29 -35 -40 -45 29 90 30 100 33 -46 +29 < 2:1 10:1 40 200 -44 1910
Unit
Condition
T=25C, VCC =3.4V unless otherwise specified
30 26 26
34
MHz MHz MHz dB dB dBc dBc dBc dBm mA dBc dBm
Output Matching Network Tune Output Matching Network Tune VMODE =Low 0V to 0.5V VMODE =High 2.5V to 3.0V VMODE =High 2.5V to 3V POUT =29dBm, VCC =3.4V, VREG =2.8V
VMODE =>2.5V POUT =29dBm, VCC =3.4V, VREG =2.8V POUT =29dBm, VCC =3.4V, VREG =2.8V VCC =3.0V, VREG =2.8V
28
No Damage. s T=25C, VCC =3.4V unless otherwise specified VMODE =0V to 0.5V POUT =30dBm, VCC =3.4V, VREG =2.8V POUT =30dBm POUT =30dBm
Overall - TDMA
Idle Current TDMA Linear Efficiency TDMA ACP @ 30kHz TDMA ALT @ 60kHz 30 250 40 -29 -49 500 -28 -48 mA % dBc dBc
2-168
Rev A18 001114
RF2153
Parameter
Power Supply
Power Supply Voltage VPD Current VPD and VMODE Current Total Current (Power down) VPD "Low" Voltage VPD "High" Voltage MODE "High" Voltage MODE "Low" Voltage Stability Spurious Noise Power 3.0 3.4 10 11 0 2.8 2.8 0 3:1 20:1 <-60 -136 4.5 13 10 0.2 2.9 0.5 V mA mA A V V V V Total pins 6 and 8 Total pins 6, 7 and 8 VPD = low
Specification Min. Typ. Max.
Unit
Condition
2
POWER AMPLIFIERS
2.7 2.5
R1=1k R1=1k Inband Outband @80MHz offset
dBc dBm/Hz
Rev A18 001114
2-169
RF2153
Pin 1 2 Function VCC2 GND2 VCC1 RF IN Description Interface Schematic
Power supply for second stage and interstage match. Pins 1, 15 and 16 should be connected by a common trace where the pins contact the printed circuit board. Ground for second stage. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Power supply for first stage and interstage match. VCC should be fed See pin 4. through a 1.5nH inductor terminated with a 15pF capacitor on the supply side. RF input. An external 15pF series capacitor is required as a DC block and also provides for an input VSWR of <2:1 typical.
RF IN From Bias Network GND1
2
POWER AMPLIFIERS
3 4
VCC1
5 6
GND1 VPD1
7
VMODE
Ground for first stage. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Power Down control for first and second stages. When this pin is "low", all first and second stage circuits are shut off. When this pin is 2.8V, all first stage circuits are operating normally. VPD1 requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. For full power operation, MODE is set low. VMODE will reduce the bias current by up to 50% when set HIGH. Large Signal Gain is reduced approximately 1.5dB at 29dBm POUT and Small Signal Gain is reduced approximately 6dB. An external series resistor is optional to limit the amount of current required by the VMODE pin. Power Down control for the third stage. When this pin is "low", the third stage circuit is shut off. When this pin is 2.8V, the third stage circuit is operating normally. VPD requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 15pF high frequency bypass capacitor is recommended. Requires a 15nH inductor.
See pin 4.
8
VPD2
9 10
BIAS GND RF OUT
11 12 13 14 15 16 Pkg Base
RF OUT RF OUT 2FO VCC VCC2 VCC2 GND
RF output and power supply for final stage. This is the unmatched colRF OUT lector output of the third stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 1850MHz to 1910MHz. From Bias It is important to select an inductor with very low DC resistance with a Network 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 12. See pin 10. Same as pin 12. Second harmonic trap. Keep traces physically short and connect immediately to ground plane. This ground should be isolated from backside ground contact. Supply for bias reference and control circuits. High frequency bypassing may be necessary. Same as pin 1. Same as pin 1. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. See pin 10.
2-170
Rev A18 001114
RF2153
Application Schematic US - CDMA
VCC
2nd Interstage tuning for centering frequency response Bypassing for VCC
10 nF
10 nF
10 nF
2
Ground for 2nd Harmonic Trap
8 pF
1st Interstage tuning to match input return loss
10 pF TL3 1 1.5 nH 2 3 4 5 47 15 pF 6 7 8 16 15 14
15 pF
15 pF
13 12 TL1
12 nH*
1 pF
To match input return loss and vary gain
TL2 4.7 pF**
15 pF RF OUT 2.2**
Matching Network for optimum load impedance
15 pF RF IN
150
11 10 9 27 L4 15 nH
15 pF
Bypassing for VREG1 and VREG2
VREG
1 k VMODE
Tied together for optimum linearity * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series).
Transmission Line Length CDMA (US)
TL1 20 mils
TL2 100 mils
TL3 20 mils
Rev A18 001114
2-171
POWER AMPLIFIERS
RF2153
Application Schematic Korea - CDMA
VC
C
2 n d In te rstag e tu n in g for ce nte rin g fre qu e n cy re sp o nse
B yp assin g fo r V C C
2
POWER AMPLIFIERS
1 st In tersta g e tu ning to m a tch in p ut re turn lo ss
10 nF
10 nF
10 nF
9 pF
10 pF TL3 1 1.8 nH 2 3 4 5 47 15 pF 6 7 8 16 15 14
15 pF
15 pF
G ro un d fo r 2 n d H a rm on ic T rap
13 12 TL1
12 nH *
1.0 pF + .25 pF
T o m a tch inp u t retu rn lo ss a n d vary g a in
TL2 5.6 pF **
15 pF RF OUT 2.2 pF **
M a tching N etw o rk fo r o p tim um loa d im p e da n ce B ia s re tu rn
15 pF R F IN
180
11 10 15 nH 9 27
15 pF
B yp assin g fo r V R E G 1 an d V R E G 2
VREG 1 k VMODE
T ie d to g eth e r fo r o p tim u m lin e arity * H ig h Q in d u cto r (i.e ., C o ilcraft 0 8 05 H Q -se ries). **H ig h Q ca p a cito rs (i.e ., Joh a n so n C -se ries).
T ransm ission Line Length C D M A (K orea)
TL1 30 m ils
TL2 100 m ils
TL3 30 m ils
2-172
Rev A18 001114
RF2153
Application Schematic US - TDMA
VCC
2nd Interstage tuning for centering frequency response Bypassing for VCC
10 nF
10 nF
10 nF
2
POWER AMPLIFIERS
1st Interstage tuning to match input return loss
15 pF
10 pF TL3 1 1 nH 2 3 4 5 0 15 pF 6 7 8 16 15 14
15 pF
15 pF
Ground for 2nd Harmonic Trap
13 12 TL1
12 nH*
1 pF
To match input return loss and vary gain
TL2 4.7 pF**
15 pF RF OUT 1.8 pF**
Matching Network for optimum load impedance Bias return
15 pF RF IN
100
11 10 15 nH 9 0
15 pF
Bypassing for VREG1 and VREG2
VREG
4.7 k VMODE
Tied together for optimum linearity * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series).
Transmission Line Length TDMA (US)
TL1 20 mils
TL2 160 mils
TL3 10 mils
Rev A18 001114
2-173
RF2153
Evaluation Board Schematic US - CDMA
C7 1 uF P1-1 C2 4.7 uF + C26 10 nF C6 15 pF C4 15 pF
2
POWER AMPLIFIERS
C12 10 nF C11 8 pF
C8 10 nF
C30
TL4
TL3 1 L3 1.5 nH 2 3 4 5 R3 39 C27 15 pF C10 1 uF P2-1 R1 1 k P2-2
Tied together for optimum linearity
16
15
14
13 12 TL1
L1*
C14 1 pF C3 15 pF
TL2 C1**
J1 RF IN
50 strip
C5 15 pF
R2
11 10 6 7 8 R4 0 C13 15 pF 9
2153400 Rev. A
J2 RF OUT
C15**
L4 15 nH
P1 P1-1 1 2 VCC GND
P2 P2-1 P2-2 1 2 VREG VMODE
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series).
Board CDMA (US)
R2 () 150
C30 (pF) 10
C1 (pF) 4.7
L1 (nH) 12
C15 (pF) 2.2
Transmission Line Length CDMA (US)
TL1 20 mils
TL2 100 mils
TL3 20 mils
TL4 100 mils or > 2.7 nH inductor
2-174
Rev A18 001114
RF2153
Evaluation Board Schematic Korea - CDMA
C7 1 uF C12 10 nF C11 9 pF C8 10 nF C6 15 pF P1-1 C2 4.7 uF + C26 10 nF C4 15 pF
2
POWER AMPLIFIERS
J2 RF OUT VCC GND VREG VMODE
C30
TL4
TL3 1 L3 1.5 nH 2 3 4 5 R3 39 C27 15 pF C10 1 uF P2-1 R1 1 k P2-2
Tied together for optimum linearity
16
15
14
13 12 TL1
L1*
C14 1.5 pF C3 15 pF
TL2 C1**
J1 RF IN
50 strip
C5 15 pF
R2
11 10 6 7 8 R4 0 C13 15 pF 9
2153401 Rev.-
C15**
L4 15 nH
P1 P1-1 1 2
P2 P2-1 P2-2 1 2
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series).
Board CDMA (Korea)
R2 () 180
C30 (pF) 11
C1 (pF) 5.6
L1 (nH) 12
C15 (pF) 2.2
Transmission Line Length CDMA (Korea)
TL1 30 mils
TL2 100 mils
TL3 30 mils
TL4 100 mils or > 2.7 nH inductor
Rev A18 001114
2-175
RF2153
Evaluation Board Schematic US - TDMA
C7 1 uF P1-1 C2 4.7 uF + C26 10 nF C6 15 pF TL3 1 L3 1 nH 2 3 4 5 R3 0 C27 15 pF 6 7 8 R4 0 C13 15 pF 16 15 14 13 12 TL1 J1 RF IN 50 strip C5 15 pF R2 11 10 9
2153402A
2
POWER AMPLIFIERS
C12 10 nF C11 15 pF
C8 10 nF
C30
C4 15 pF
L1*
C14 1 pF C3 15 pF
TL2 C1**
J2 RF OUT
C15**
L4 15 nH
P1 P1-1 1 2 VCC GND
P2 P2-1 R1 4.7 k P2-2
Tied together for optimum linearity
P2-1 P2-2
1 2
VREG VMODE
* L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series).
Board TDMA (US)
R2 () 100
C30 (pF) 10
C1 (pF) 4.7
L1 (nH) 12
C15 (pF) 1.8
Transmission Line Length TDMA (US)
TL1 20 mils
TL2 160 mils
TL3 10 mils
2-176
Rev A18 001114
RF2153
Evaluation Board Layout US - CDMA Board Size 2.0" x 2.0"
Board Thickness 0.031", Board Material FR-4
2
POWER AMPLIFIERS
Evaluation Board Layout Korea - CDMA
Rev A18 001114
2-177
RF2153
Evaluation Board Layout US - TDMA
2
POWER AMPLIFIERS
2-178
Rev A18 001114

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